The Toolbox — Symbols

Logic Gates

Standard logic gate symbols with truth table expressions, descriptions, and common applications.

Basic Gates

BufferQ = APasses the input directly to the output without inversion. Used to boost drive strength or add propagation delay.

NOT Gate (Inverter)Q = ĀInverts the input. Output is HIGH when input is LOW and vice versa. The bubble on the output indicates inversion.

AND GateQ = A · BOutput is HIGH only when ALL inputs are HIGH. Used for condition checking where all conditions must be true simultaneously.

OR GateQ = A + BOutput is HIGH when ANY input is HIGH. Used for condition checking where at least one condition must be true.

XOR GateQ = A ⊕ BOutput is HIGH when inputs are DIFFERENT. Also called exclusive OR. Used in binary adders, parity generators, and comparators.

Inverted Gates

NAND GateQ = ‾A·BAND gate with inverted output. Output is LOW only when ALL inputs are HIGH. Universal gate — any logic function can be built from NAND gates alone.

NOR GateQ = ‾A+BOR gate with inverted output. Output is HIGH only when ALL inputs are LOW. Also a universal gate like NAND.

XNOR GateQ = ‾A⊕BXOR gate with inverted output. Output is HIGH when inputs are EQUAL. Used in equality comparators and parity checkers.

Flip-Flops

D Flip-FlopQ(n+1) = DData or Delay flip-flop. Output Q takes the value of input D on the rising edge of the clock. Used for data storage and pipeline registers.

JK Flip-FlopQ(n+1) = J·Q̄ + K̄·QVersatile flip-flop with J (Set) and K (Reset) inputs. When both J and K are HIGH, output toggles on each clock edge.

SR LatchQ = S + R̄·QSet-Reset latch. S=1 sets Q HIGH, R=1 resets Q LOW. S=R=1 is a forbidden state. Asynchronous — no clock required.

Combinational Logic

Multiplexer (MUX)Q = S·B + S̄·ASelects one of multiple input signals and routes it to the output based on select inputs. A 2:1 MUX selects between 2 inputs using 1 select line.

Demultiplexer (DEMUX)Routes 1→NRoutes one input signal to one of several outputs based on select inputs. The inverse of a MUX.

Half AdderS = A⊕B, C = A·BAdds two single bits producing a Sum and Carry output. Does not handle carry-in from previous stage.

Tri-State BufferQ = A if EN=1, Hi-Z if EN=0Buffer with a third high-impedance (Hi-Z) state. When disabled, output disconnects from the bus. Essential for shared bus architectures.

Note: Symbols shown follow ANSI/IEEE standard (distinctive shape). IEC standard uses rectangular symbols with function labels inside. Both are in common use depending on region and application.